The present invention relates in general to switched capacitor circuits and in particular to circuits and methods for latch metastability detection and compensation and systems using the same.
One particular technique for performing analog to digital (A/D) conversion is through successive approximation. The basic successive approximation A/D converter (ADC) includes an analog comparator and a clocked feedback loop having a successive approximation register (SAR) and a digital to analog converter (DAC).
Generally, the analog input signal voltage is sampled onto an array of weighted capacitors, during the sampling phase, the top plates of which are coupled to one comparator input. The other comparator input is coupled to a comparison voltage, which could be a fixed reference voltage in a single-ended system or the voltage at the top plates of second capacitor array in a differential system.
During the first clock cycle of the subsequent conversion phase, the bottom plate of the capacitor representing the digital most significant bit (MSB) is coupled to a reference voltage while the bottom plates of the remaining capacitors in the array are coupled to ground or a second reference voltage (ground will be assumed here). The new top plate voltage appears at the input of the comparator and is compared against the comparison voltage. The new top plate voltage is a scaled version of       [                  Voef        2            -      ain        ]    ·  k
where k is the ratio of capacitors. The sign of this quantity is the factor of interest. If the new top plate voltage is below the comparison voltage, then the MSB is xe2x80x9ckeptxe2x80x9d by the SAR in the feedback loop by maintaining its bottom plate coupled to the reference voltage. On the other hand, if the top plate voltage is above the comparison voltage, the SAR couples and the bottom plate of the MSB capacitor to ground. The state of the MSB capacitor represents the MSB of the digital output word as a Logic 1. The bottom plate of the second MSB is then coupled to the reference voltage and the same test is performed to determine the state of the next digital code bit. The successive approximation algorithm continues by repeating this procedure for the remaining capacitors in the array such that the voltage difference at the inputs to the comparator converge to zero. At the end of this bit cycling process, the configuration of the switches coupling the bottom plates either to Vref or Gnd represents the input sample in digital form.
Successive approximation A/D converters are useful a wide range of applications, including data acquisition, test equipment, instrumentation, cellular communications, among others. Notwithstanding, in order to improve and broaden the utility of this type of A/D converter, significant challenges remain to be addressed. These challenges include improving the device speed given a set of process constraints, reducing the coding error rate, handling metastable states and calibration of the DAC.
Principles of the present invention are disclosed in circuits and methods for detecting and compensating for metastability in a regenerative latch. These circuits are particularly useful in charge redistribution analog to digital converters and similar high performance application, although not necessarily limited thereto.
According to one embodiment of the present inventive concepts, metastability compensation circuitry is disclosed for detecting and compensating for metastable states of a regenerative latch in a charge redistribution analog to digital converter. First and second latches each have a selected threshold voltage monitor corresponding first and second outputs of the regenerative latch. Detection and suppression logic detects a selected output state of the first and second latches corresponding to a metastable state of the regenerative latch and generates an output of a selected logic level in response.
Metastability in regenerative latches can present a significant problem in high performance applications such as analog to digital converters. Specifically, metastability can increase the conversion error rate, especially at high data conversion rates, to unacceptably high levels. The present inventive principles allow for the detection of metastable states in such a latch as well as for the compensation of the detected error in the resulting digital output code.